1. Field of the Invention
The present invention relates to a digital image signal decoding apparatus having a frame memory for motion compensation.
2. Description of the Related Art
In the past, as for the apparatus for decoding a digital image such as MPEG (Motion Picture Experts Group)-4, an image signal decoding apparatus having a frame memory for performing motion compensation was known.
FIG. 11 is a diagram showing a configuration of an image signal decoding apparatus 100 used in the past. In FIG. 11, the image signal decoding apparatus 100 includes and is comprised of a buffer 101, a variable length decoding division (hereafter, referred to as “VLD”) 102, an AC/DC (Alternating Current or Direct Current) predicting division 103, an inverse quantization division 104, an inverse DCT (Discrete Cosine Transform) division 105, a frame memories 106a and 106b, a motion compensation processing division 107, an adder 108, a format conversion division 109 and a D/A (Digital to Analog) converter 110.
The buffer 101 temporarily stores data included in an input signal and outputs it to the VLD 102.
The VLD 102 decodes in variable length the data inputted from the buffer 101, and outputs the decoded data (hereafter, referred to as “variable length decoded data”) to the AC/DC predicting division 103 and the motion compensation processing division 107.
The AC/DC predicting division 103 predicts AC and DC components of the variable length decoded data inputted from the VLD 102 between or inside the frames, and outputs predictive data (hereafter, referred to as “predictive data”) to the inverse quantization division 104.
The inverse quantization division 104 inversely quantizes the predictive data inputted from the AC/DC predicting division 103, and outputs inversely quantized data (hereafter, referred to as “inversely quantized data”) to the inverse DCT division 105.
The inverse DCT division 105 performs inverse discrete cosine transform to the inversely quantized data inputted from the inverse quantization division 104, and outputs transformed data (hereafter, referred to as “inverse DCT data”) to the adder 108.
As for the frame memories 106a and 106b, one of them stores frame data of a frame immediately preceding the currently decoded frame (hereafter, referred to as “forward reference frame data”), and the other stores the frame data of the currently decoded frame (hereafter, referred to as “current frame data”) according to an instruction of the motion compensation processing division 107. These two frame memories have the frame data processed by the decoding apparatus 100 alternately stored frame by frame. And then, of the frame data stored in the frame memories 106a and 106b, the forward reference frame data is outputted to the motion compensation processing division 107 to be used for the motion compensation processing.
The motion compensation processing division 107 performs the motion compensation process by macro blocks based on the forward reference frame data stored in one of the frame memories 106a and 106b and the variable length decoded data inputted from the VLD 102, and outputs processing results (hereafter, referred to as “motion compensation data”) to the adder 108. In addition, the motion compensation processing division 107 outputs an instruction signal to the frame memories 106a and 106b to have each frame memory store the current frame data or store the forward reference frame data to be used for the motion compensation process each time one frame is processed.
The adder 108 adds the inverse DCT data inputted from the inverse DCT division 105 to the motion compensation data inputted from the motion compensation processing division 107, and outputs addition results to the format conversion division 109. In addition, the adder 108 outputs the addition results to the frame memory, of the frame memories 106a and 106b, which is supposed to store the processing results of the current frame data according to the motion compensation processing division 107.
The format conversion division 109 converts the addition results inputted from the adder 108 into a predetermined data format, and outputs it to the D/A converter 110.
The D/A converter 110 D/A-converts the data in the predetermined format inputted from the format conversion division 109, and outputs it as an analog image signal.
As the above-mentioned decoding apparatus 100 refers to the forward reference frame when performing the motion compensation process, it has, for the sake of constantly storing the forward reference frame data, two frame memories provided therein, that is, one for storing the forward reference frame data and the other for storing the current frame data.
Here, as the frame memories used for decoding image signals need to have a high speed, a high-speed device such as an SRAM (Static Random Access Memory) of a short access time is used. Accordingly, in the case of having two frame memories, the image signal decoding apparatus requires high cost. In addition, in the case of performing the motion compensation process while having two frame memories, it consumes large amounts of electric power in order to store the frame data in the frame memories.
To solve these problems, Japanese Patent Laid-Open No. 6-205395 or the like discloses the image signal decoding apparatus having one frame memory, a FIFO (First In First Out)-type memory and a memory controller for controlling them.
FIG. 12 is a diagram showing an example of the configuration of an image signal decoding apparatus 200 having the FIFO-type memory. In FIG. 12, the image signal decoding apparatus 200 has a FIFO-type memory 206a, a frame memory 206b and a memory controller 206c instead of the frame memories 106a and 106b of the image signal decoding apparatus 100. As for the image signal decoding apparatus 200 shown in FIG. 12, the portions other than the FIFO-type memory 206a, frame memory 206b and memory controller 206c are the same as those of the image signal decoding apparatus 100 shown in FIG. 11 so that they are numbered likewise and description thereof is omitted. In addition, it will be described hereafter by referring to the description of the portions that are the same as and corresponding to those of the image signal decoding apparatus 100.
In FIG. 12, the FIFO-type memory 206a stores the addition results of the adder 108, and outputs them to the frame memory 206b in order of input in predetermined timing. In addition, in the case where the motion compensation processing division 107 performs the motion compensation process, the FIFO-type memory 206a outputs the predetermined data used for the motion compensation, of the frame data that is stored, to the motion compensation processing division 107. Moreover, the FIFO-type memory 206a stores eight slices in the image of one frame, where a “slice” is comprised of one horizontal row of macro blocks. Storage capacity is eight slices because a vertical range of the motion compensation is eight slices at the maximum in the MPEG-1 standard.
The frame memory 206b stores the frame data preceding the frame currently decoded by the image signal decoding apparatus 200. If the predetermined frame data of the currently decoded frame is inputted from the FIFO-type memory 206aaccording to an instruction of the memory controller 206c, however, the frame memory 206b overwrites with the inputted frame data the forward reference frame data of the same in-frame address as that data.
The memory controller 206c outputs to the FIFO-type memory 206a the instruction signal for having the most previously stored data of one slice outputted to the frame memory 206b. In addition, the memory controller 206c outputs to the frame memory 206b the instruction signal for having the data of one slice inputted from the FIFO-type memory 206a written to the predetermined address.
At this time, the memory controller 206c has the inputted data overwritten with the same in-frame address in the forward reference frame stored in the frame memory 206b. To be more specific, in the frame memory 206b, the forward reference frame data is maintained as to the data of the addresses within eight slices of the frame data currently decoded in the image signal decoding apparatus 200, and the data of the addresses apart by nine or more slices is sequentially overwritten.
As for the above-mentioned image signal decoding apparatus having the FIFO-type memory, however, there may be the cases where the image based on the MPEG-4 standard has a motion compensation range covering the entire image so that the decoding process cannot be appropriately performed when the storage capacity of the FIFO-type memory is limited to eight slices.